Modelling and verifying synchronous circuits in DILL :: Ji He :: Dept. of Computing Science and Mathematics, University of Stirling 1999 :: OBNB, the Open British National Bibliography

Publication Data

Title Modelling and verifying synchronous circuits in DILL
Author Ji He
Contributors Kenneth J. Turner, Kenneth J. Turner
Publisher Dept. of Computing Science and Mathematics, University of Stirling
Publication date 1999
Publication location Stirling
Language English

Topics

Integrated circuits :: Verification
Logic circuits

Catalogue Data

OBNB ID GB9981704
ISBN 10 n/a
ISBN 13 n/a
Type BibliographicResource, Book

ISBD

P1053 iv,21p.
P1042 Includes bibliographical references.

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Modelling and verifying synchronous circuits in DILL by Ji He. Published by Dept. of Computing Science and Mathematics, University of Stirling in 1999. Publication and catalogue information, links to buy online and reader comments.